1. Field of the Invention
This invention relates to a semiconductor chip package, and more particularly to a chip package structure with better heat dissipation and less warpage of the package substrate.
2. Brief Description of Related Art
In the semiconductor industry, the production of integrated circuits (ICs) includes three stages: wafer production, IC production and IC package. A bare chip (die) is obtained after forming a plurality of semiconductor devices on a wafer and singulating the wafer. The singulated bare chip is electrically connected to an external device via contacts and then encapsulated by the molding compound. The package structure of the chip can protect the bare chip from influences of external moisture, heat, and noise, and acts as a medium for electrically connecting the bare die and the external circuitry.
Flip chip bonding technology distributes bonding pads over an active surface of a chip in area arrays, and turns (flips) the chip upside down to attach onto a carrier after bumps has been formed respectively on the bonding pads. The bumps electrically and physically connect bonding pads of the chip to the contacts of the substrate so that chip is electrically connected to the substrate via the bumps and can be further connected to external devices through an inner wiring of the substrate.
It is noted the flip chip technology can be applied to high-pin-count semiconductor package structures. Moreover, because of its advantages such as small package area and short signal transmission path, flip chip technology has been widely applied in the semiconductor package. One of the most common flip-chip package structures is the flip chip ball grid array (FC/BGA) type package structure. As the operation speed of the chips keeps increasing, higher requirement of heat dissipation accordingly is desired.
FIG. 1 is a side view of a conventional FC/BGA chip package structure 100. Bumps 106 electrically connect a chip 102 and a substrate 104. In other words, bodning pads (not shown) on the chip 102 electrically connect to electrode pads (not shown) on the substrate 104 via the bumps 106. An underfill 108 is filled between the chip 102 and the substrate 104. The underfill 108 provides stress buffer to protect the bumps 106 between the chip 102 and the substrate 104 from damages due to mismatch in coefficients of thermal expansion (CTE). A stiffener ring 110 is disposed on the substrate 104 and around the chip 102. A heat sink 112 locates on the stiffener ring 110 and on the back side of the chip 102. Furthermore, solder balls 114 are further mounted on another surface of the substrate 104 opposite to the chip carrying surface of the substrate 104. The bonding pads of the chip 102 electrically connect to solder balls 114 via an internal wiring of the substrate 104.
However, for the chip package structure of FIG. 1, during thermal cycles or reliability tests of equipment that is installed with such package structure, the package structure tends to warp or deform, due to the CTE mismatch between the chip and the substrate (CTE of the chip is about 2.6 ppm/° C. and that of the substrate is about 15–18 ppm/° C.). Sometimes in serious cases, bumps in the package structure even detach from the substrate as shown in FIG. 2. Such a deformation becomes significant when the size of the chip becomes approximate to that of the substrate; for example, when the chip is 19*23 mm and the substrate is 27*27 mm.